1. Field of the Invention
The present invention relates to a crystallizing method, and more particularly, to a mask and method for crystallizing amorphous silicon. Although the present invention is suitable for a wide scope of applications, it is particularly suitable for improving fabrication productivity.
2. Discussion of the Related Art
A liquid crystal display (LCD) device has been in the spotlight as a next generation high value display device because of its low power consumption and portability.
The liquid crystal display device is composed of an array substrate including thin film transistors, a color filter substrate, and a liquid crystal layer interposed between an array substrate and a color filter substrate. The liquid crystal display device displays images by using transmittance of light depending on the anisotropic refractive index of the liquid crystal layer.
An active matrix liquid crystal display (AMLCD) device, which includes a thin film transistor at each pixel as a switching device, has been widely used due to its high resolution and fast moving images.
In general, silicon has been used as an active layer of the thin film transistor. Especially, since polycrystalline silicon has a high field effect mobility and is optically stable, it has been widely used as an active layer of a thin film transistor for a liquid crystal display device having driving circuits and thin film transistors on the same substrate or for a display device that is much exposed to light.
Polycrystalline silicon may be formed through a high temperature process or a low temperature process. The high temperature process may be accomplished under the temperatures of about 1,000 degrees Celsius, which are much higher than the transition temperature of an insulating substrate, such as a glass substrate. Therefore, the high temperature process requires a quartz substrate that has a high heat resistance. However, the quartz substrate may not be cost effective for a substrate of thin film transistors. In addition, a polycrystalline silicon layer formed through the high temperature process has a high surface roughness and comprises fine grains.
Accordingly, a method of forming polycrystalline silicon, which includes depositing amorphous silicon that can be formed under low temperature conditions and crystallizing the amorphous silicon, has been researched and developed. The method of forming polycrystalline silicon includes a laser annealing method and a metal induced crystallization method.
Among these methods, in the laser annealing method, pulses of laser beams are irradiated on a substrate including an amorphous silicon layer, and melting and solidification of the irradiated amorphous silicon layer are repeatedly accomplished in 10 to 102 nanoseconds. Thus, damage to the substrate under the silicon layer may be minimized.
A method of crystallizing amorphous silicon will be described in detail with reference to the attached drawings.
FIG. 1 is a graph showing an energy intensity of a laser beam versus a grain size of crystallized silicon in a laser annealing method.
In FIG. 1, a first region of the graph is a partial melting regime. Only the surface of a silicon layer is melted by the energy intensity of the first region, thereby forming small grains.
A second region of the graph is a near-complete melting regime. Grains formed in the second region are larger than those in the first region because the grains laterally grow. However, sizes of the grains are non-uniform.
A third region of the graph is a complete melting regime, wherein an amorphous silicon layer is entirely melted by the energy intensity of the third region and fine grains are formed due to homogeneous nucleation.
Thus, in the laser annealing method, in order to form uniform and large grains, the energy intensity of the second region may be used, and irradiation times and overlapping ratios of the laser beams may be controlled.
Generally, grain boundaries of polycrystalline silicon interfere with currents and lowers the reliability of a thin film transistor. In addition, a breakdown of an insulating layer may occur because of a collision of electrons and a deterioration in the grains.
Accordingly, the formation of single crystalline silicon is important, and recently, a sequential lateral solidification (SLS) method has become of interest to solve the above problems. The SLS method takes advantage of the fact that silicon grains grow laterally from the boundary between the liquid silicon and the solid phase silicon. The SLS method can increase the size of the silicon grains by controlling the energy intensity of a laser beam and the irradiation range of the laser beam. The SLS method is disclosed in Robert S. Sposilli, M. A. Crowder, and James S. Im, Mat. Res. Soc. Symp. Proc. Vol. 452, 956˜957, 1997. TFTs having channel areas of single crystalline silicon can be formed by the SLS method.
FIG. 2 is a schematic view showing the SLS crystallizing method using a laser annealing process according to the related art. In FIG. 2, a crystallizing mask 14, which includes slits 12 spaced apart from each other, is disposed over a silicon layer 10 of an amorphous phase. A laser beam 16 is irradiated on portions A of the silicon layer 10 through the slits 12 of the crystallizing mask 14. The laser beam 16 has an energy intensity that can completely melt the silicon layer 10 exposed to the laser beam 16. Thus, the portions A of the silicon layer 10 corresponding to the slits 12 are completely melted. Then, a plurality of grains 18 grow laterally from the boundaries of the melted portions A of the silicon layer 10, and the growth of the grains 18 stop at region B where the grains 18 meet each other. A width from one boundary of the portion A to the region B where the growth of the grains 18 stop may be referred to as length L of the grain 18.
Although not shown in FIG. 2, the crystallizing mask 14 can be moved laterally so that the slit 12 may overlap one of the boundaries of the portion A. A laser beam is irradiated on the next portion of the silicon layer 10, which overlaps the portion A, and the next portion is crystallized. Thus, larger grains are formed by repeatedly accomplishing the above processes.
The processes are performed until the length of the grain is about 10 micrometers (μm), and the silicon layer including the grains may be used as an active layer of a thin film transistor, which has a channel of about 6 micrometers (μm) in width.
FIG. 3 schematically shows a mask for crystallizing according to the related art.
As shown in FIG. 3, a plurality of blocking layers 22 spaced apart from each other is formed on a base substrate 20. Spaces between the blocking layers 22 are defined as slits 24. The base substrate 20 may be formed of quartz, and the blocking layers 22 may be formed of chromium (Cr), which reflects a laser beam. The blocking layers 22 may have a width of about 4 micrometers (μm), and the slits 24 may have a width of about 2 micrometers (μm).
FIG. 4 shows overlaps between shots of a laser beam in the SLS crystallizing process using the mask of FIG. 3. A profile of the laser beam at each shot relates to an energy intensity of the laser beam. FIG. 4 illustrates the region corresponding to only two slits of the mask for simplicity.
As shown in FIG. 4, a first laser shot is irradiated on the substrate 28 including an amorphous silicon layer 26 thereon, and a beam passing through the mask has two peaks corresponding to the slits. Second, third, and fourth laser shots are subsequently irradiated such that peaks of each laser shot overlap each other. At this time, the peaks overlap each other such that the overlapping portions between the peaks can have energy intensities higher than the melting point of the silicon layer 26.
The peaks of the first laser shot to the fourth laser shot overlap each other with a fixed width because a position of the substrate 20 corresponding to the slit of the mask changes by moving the substrate in a first direction in FIG. 4. In FIG. 4, a second direction, which is opposite to the first direction, indicates the growing direction of the grains.
Although not shown in FIG. 4, distance C between the two peaks of the first laser shot is closely connected to the width of the blocking layer 22 of the mask 20 of FIG. 3 (i.e., a space between the slits 24 of FIG. 3). Since the peaks of each laser shot must have the distance C therebetween to prevent them from overlapping each other, there is a limitation in reducing the width of the blocking layer 22 under 4 micrometers (μm) according to the structure of the mask of the related art.
More particularly, in the SLS crystallizing process using the mask of the related art, if the peaks of a laser shot overlap each other, the silicon layer is melted non-uniformly because an overlapping portion between the peaks is large, and thus the grains do not grow completely. In addition, since a nucleation region is formed in the overlapping portion, characteristics of crystallization get worse. Therefore, the width of the blocking layer, that is, the space between the slits must be more than at least 4 micrometers (μm) so that the peaks of each laser shot do not overlap each other, thereby providing a reliable process. However, there is a disadvantage in that the efficiency of the process is lowered due to an increase in the laser shots.